1. Field of the Invention
The present invention relates to bus driver circuits and more particularly to bus hold circuits that maintain the output logic state when the source of the input signal assumes a high impedance state; and more particularly to CMOS bus hold circuitry that is over voltage tolerant, that does not create a leakage path when powered down, and is frugal of DC power and components.
2. Background Information
Traditional bus hold circuits latch data from an input connection while providing a high impedance load on the input connection. Older bus hold circuits have neither power-down nor over-voltage tolerance and faulty or unacceptable conditions may occur under such circumstances. Over voltage will occur when, for example, a +5 volt logic system interfaces with a +3.3 V system, or transiently when severe input signal over-shoots occur. Power down situations happen when a portion of a system is unpowered, say for maintenance purposes, or to conserve battery life. In such occurrences, leakage currents may unacceptably load the input signal. Such limitations are addressed by the present invention.
FIG. 1A illustrates one limitation of the prior art circuits. The circuit inverter output is connected back via an inverter, PMOS and NMOS, to latch and thereby hold the input data. But, from inspection when the input signal is driven from a +5V logic level but the Vcc is +3.3V (or +1.8V) a leakage path exists through the drain to N-well diode, illustrated as D1. If the input voltage exceeds the Vcc, undesirable current will be drawn from the input signal connection and the latch circuit may malfunction. FIG. 1B shows the N-well to source leakage path in a sectioned view of a PMOS device, the leakage diode represented by D1.
Others have addressed some shortcomings of prior art bus hold circuits. U.S. Pat. No. 5,828,233 to Nguyen et al. (Nguyen) describes a circuit that provides both power-down and over-voltage protection tolerance. Nguyen employs passive components and two diode connected NMOS transistors arranged parallel anode to cathode, N3 and N4. Each of these diode connected transistors display about a 0.6V drop that have to be over-come before the circuit responds. Since the diodes are in parallel there is about a 1.2V zone (from one diode being on to the other diode being on) where the circuit operation is undetermined, ambiguous and asymmetrical. This 1.2V range is unacceptable. Asymmetrical is defined herein to mean that operation of the bus hold circuit displays markedly different delay/drive/noise level parameters under different input drive signals.
U.S. Pat. No. 6,097,229 to Hinterscher (Hinterscher) describes a circuit that is power-down tolerant but has no power-up or over-voltage tolerance.
U.S. Pat. No. 6,150,845 to Morrill (Morrill), which is commonly owned with the present application, describes a bus hold circuit with both power-down, over-voltage tolerance, and that prevents leakage from the input/output pins. But, the circuit undesirably contains many devices and consumes DC power in order to sense the over-voltage occurrence.
The Nguyen, Hinterscher and Morrill patents are each incorporated herein by reference.
It is an objective of the present invention to provide a bus hold circuit for use in computer, communications, interfacing and generally in virtually any digital system where symmetrical operation is desirable, and where such digital systems exhibit: power-down and over-voltage tolerance; economy of devices; and virtually no DC power consumption.
In view of the foregoing background discussion, the present invention provides a bus hold circuit, powered from Vcc, that addresses the limitations of the prior art.
The invention provides a CMOS inverter with a latching feedback inverter that includes a first PMOS device that selectively powers the second inverter. The N-well of this first PMOS device is connected to a pseudo power rail or prail. An arbiter circuit connects the more positive of the input voltage or the Vcc to the prail. This arrangement prevents the drain to N-well junction of this first PMOS device from becoming forward biased if Vin exceeds Vcc.
A comparator circuit provides a control signal of Vin, when Vin is at a higher potential than Vcc. The comparator circuit disconnects the control signal allowing it to float when Vcc is higher. When Vin is low, a second PMOS switch pulls the control signal low.
The N-wells of the PMOS devices in the bus bold circuit are connected to the prail provided by the arbiter circuit so that none of the PMOS devices will form a leakage path when Vin exceeds Vcc.
The comparator circuit, the first PMOS device, and the second PMOS switch acting together with the entire bus hold circuitry reduce the window of uncertainty between Vcc and Vin to about 100 millivolts.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.